Astera Labs
Slug:
asteralabs
Domain: asteralabs.com
Industry: semiconductors
· Technology
Size: 201-500
Jobs (FK): 520
Website: asteralabs.com
·
Careers page
Company profile
- HQ
- santa clara , california , United States
- Social
520 jobs for this company
| ID | Title | Location | Country | State | Workplace | Status | Employment | Salary min | Salary max | Currency | Period | First seen | Posted | Last seen | Contacts | Link |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 45278679 | Tech Lead, Analog Mixed Signal Layout | Ho Chi Minh City, Vietnam | Vietnam | — | Onsite | active | — | — | — | — | — | Sept. 30, 2026, 12:41 a.m. | Sept. 29, 2026, 2:35 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 45278638 | Senior Manager, Digital Design | San Jose, California, United States | United States | CA | Onsite | active | — | 216000.0 | 240000.0 | USD | — | Sept. 30, 2026, 12:41 a.m. | Sept. 29, 2026, 3:25 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 45278618 | Principal Verification Engineer | San Jose, California, United States | United States | CA | Onsite | active | — | 185000.0 | 230000.0 | USD | — | Sept. 30, 2026, 12:41 a.m. | Sept. 29, 2026, 1:01 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 45278583 | Principal Electrical Engineer – Smart Cable Modules | San Jose, California, United States | United States | CA | Onsite | active | — | 185000.0 | 240000.0 | USD | — | Sept. 30, 2026, 12:41 a.m. | Sept. 29, 2026, 8:37 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 45278520 | AE| Principal Product Application Engineer (Scorpio) | San Jose, California, United States | United States | CA | Onsite | active | — | — | — | — | — | Sept. 30, 2026, 12:41 a.m. | Sept. 29, 2026, 1:23 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 44646341 | Tech Lead Engineer, Design Verification | San Jose, California, United States | United States | CA | Onsite | active | — | 175500.0 | 195000.0 | USD | — | Sept. 29, 2026, 12:38 a.m. | Sept. 28, 2026, 9:12 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 44646340 | Tech Lead, Digital Design Engineer | San Jose, California, United States | United States | CA | Onsite | active | — | — | — | — | — | Sept. 29, 2026, 12:38 a.m. | Sept. 28, 2026, 9:43 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 44646294 | Senior Digital Design Engineer | San Jose, California, United States | United States | CA | Onsite | active | — | — | — | — | — | Sept. 29, 2026, 12:38 a.m. | Sept. 28, 2026, 9:40 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 44646290 | Senior Design Verification Engineer | San Jose, California, United States | United States | CA | Onsite | active | — | 148500.0 | 165000.0 | USD | — | Sept. 29, 2026, 12:38 a.m. | Sept. 28, 2026, 9:15 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 44646234 | Principal Analog Mixed-Signal Design Engineer | Ho Chi Minh City, Vietnam | Vietnam | — | Onsite | active | — | — | — | — | — | Sept. 29, 2026, 12:38 a.m. | Sept. 28, 2026, 2:46 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 43038928 | Senior Principal Program Manager, Business Acceleration | San Jose, California, United States | United States | CA | Onsite | active | — | 205000.0 | 260000.0 | USD | — | Sept. 26, 2026, 12:36 a.m. | Sept. 25, 2026, 9:57 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 43038856 | Principal Analog Mixed-Signal Design Engineer | Irvine, California, United States | United States | CA | Onsite | active | — | 170000.0 | 210000.0 | USD | — | Sept. 26, 2026, 12:36 a.m. | Sept. 25, 2026, 4:33 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 43038854 | Principal Analog Mixed-Signal Design Engineer | Toronto, Ontario, Canada | Canada | — | Onsite | active | — | 165000.0 | 210000.0 | USD | — | Sept. 26, 2026, 12:36 a.m. | Sept. 25, 2026, 5:16 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 42432850 | Principal Field Applications Engineer | Shanghai Shi, China | China | — | Onsite | active | — | — | — | — | — | Sept. 25, 2026, 12:37 a.m. | Sept. 24, 2026, 3:53 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 42432809 | HR Operations Specialist | San Jose, California, United States | United States | CA | Onsite | active | — | 117000.0 | 130000.0 | USD | — | Sept. 25, 2026, 12:37 a.m. | Sept. 24, 2026, 7:02 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 41374325 | Silicon Digital IP / Subsystem Architect | Bengaluru, Karnataka, India | India | — | Onsite | active | — | — | — | — | — | Sept. 23, 2026, 12:40 a.m. | Sept. 22, 2026, 9:46 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 41374305 | Senior Packaging Integration Lead | San Jose, California, United States | United States | CA | Onsite | active | — | — | — | — | — | Sept. 23, 2026, 12:40 a.m. | Sept. 22, 2026, 9:58 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 41374274 | Principal Product Applications Engineer | Shanghai Shi, China | China | — | Onsite | active | — | — | — | — | — | Sept. 23, 2026, 12:40 a.m. | Sept. 22, 2026, 6:34 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 41374226 | Lead Logic Design Engineer | Bengaluru, Karnataka, India | India | — | Onsite | active | — | — | — | — | — | Sept. 23, 2026, 12:40 a.m. | Sept. 22, 2026, 6 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 41374225 | Lead Logic Design Engineer | Bengaluru, Karnataka, India | India | — | Onsite | active | — | — | — | — | — | Sept. 23, 2026, 12:40 a.m. | Sept. 22, 2026, 6 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 40851504 | Senior Engineer PD | Singapore, Singapore | Singapore | — | Onsite | active | — | — | — | — | — | Sept. 22, 2026, 12:39 a.m. | Sept. 21, 2026, 8:43 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 40851397 | DFT Engineer | Bengaluru, Karnataka, India | India | — | Onsite | active | — | 133200.0 | 185000.0 | USD | — | Sept. 22, 2026, 12:39 a.m. | Sept. 21, 2026, 6:18 a.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 40851395 | Design Verification Tech Lead- SerDes/PHY IP | San Jose, California, United States | United States | CA | Onsite | active | — | 160000.0 | 200000.0 | USD | — | Sept. 22, 2026, 12:39 a.m. | Sept. 21, 2026, 11:14 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 39138187 | Tech Lead PCB Layout Engineer | Shanghai Shi, China | China | — | Onsite | active | — | — | — | — | — | Sept. 19, 2026, 12:38 a.m. | Sept. 18, 2026, 4:43 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |
| 38666223 | Principal Logic Design Engineer - UALink IP/Subsystem | Bengaluru, Karnataka, India | India | — | Onsite | active | — | — | — | — | — | Sept. 18, 2026, 12:41 a.m. | Sept. 17, 2026, 12:31 p.m. | Sept. 30, 2026, 12:41 a.m. | — | Open |